The present invention relates to a method for manufacturing a semiconductor device, and, more particularly, to a method for planarizing a layer.
A chemical mechanical polishing (CMP) process has been increasingly adopted in the manufacture of semiconductor devices as the degree of integration in semiconductor devices increases. Planarization based on the CMP process is used as one of the methods to prevent the generation of steps on respective regions of a highly integrated semiconductor device. As use of the CMP process increases, making improvements in polishing uniformity during the CMP process and thickness uniformity in a polished layer becomes important matters.
To improve planarization degree and polishing uniformity, research has focused mainly with the process parameters of the CMP process. For example, adjustment of the process parameters can be obtained by changing the kind of slurry used to polish the target layer deposited on a wafer or substrate, controlling the content of the slurry, replacing or modifying components of the CMP apparatus (e.g., the conditioner), adjusting the RPMs used in polishing, or adjusting the compressive force of the head. With the adjustments of these process parameters, various attempts have been made to improve the planarization degree and thickness uniformity of the layer.
Without considering the properties of the polishing target layer, attempts at adjusting the process parameters may lead to problems. Thus, it may be considered that a high degree of thickness uniformity or planarization required for the manufacture of the semiconductor device cannot be obtained only through the adjustment of the process parameters for the CMP process as described above.
In some cases, the thickness uniformity of the polishing target layer may be worse off after the CMP process has been performed. In the case of an oxide layer formed by high density plasma deposition (HDP), the central region of the wafer may likely have a thinner deposition thickness than the outer regions. The conventional CMP process generally uses ceria-based slurry, which provides a relatively high polishing rate near the central region of the wafer. Thus, when the conventional CMP process is performed on the HDP oxide layer, the polishing only increases the inconsistent thickness caused by the deposition.